NVIDIA's Vera CPU: A New Variable in ARM Server Selection
In July 2026, NVIDIA released a significant amount of new technical information on its upcoming Vera CPUs and Rubin GPUs, including a full architectural whitepaper for Vera and fresh SPEC CPU 2026 benchmark figures. Vera is NVIDIA's first custom CPU core architecture in years (codenamed Olympus). Its significance: NVIDIA is no longer content to make a CPU that simply drives its own GPUs (as with Grace) — it wants Vera to enter the broader server CPU market.
For the past few years, NVIDIA's server CPU role has been fairly "dedicated": Grace appeared mainly as the companion chip for Grace-Hopper supercomputer nodes, supplying memory and interconnects around the GPU. Vera changes that narrative — it is a full-fledged general-purpose ARM server processor standing on the same track as Intel Xeon, AMD EPYC, and Arm-based chips such as AWS Graviton.
What Vera is
Compared with Grace, Vera is a full step up as an Arm-based server processor:
| Feature | Grace | Vera |
|---|---|---|
| CPU Architecture | Arm Neoverse V2 | NVIDIA Olympus |
| Cores | 72 | 88 |
| Threads | 72 | 176 (Spatial Multithreading) |
| L2 Cache per core | 1MB | 2MB |
| Unified L3 Cache | 114MB | 164MB |
| Memory bandwidth | Up to 512GB/s | Up to 1.2TB/s |
| Memory capacity | Up to 480GB LPDDR5X | Up to 1.5TB LPDDR5X |
| SIMD | 4x 128b SVE2 | 6x 128b SVE2 FP8 |
| NVLink-C2C | 900GB/s | 1.8TB/s |
| PCIe/CXL | Gen5 | Gen6/CXL 3.1 |
| TDP | 250W | 250-450W |
Architecture highlights: the Olympus core
- A powerful front-end: a neural branch predictor that outputs 2 branches per cycle; an instruction fetch unit that feeds up to 16 64-bit instructions into the decode queue per cycle, with a 48-entry queue and a decoder that emits up to 10 fused instructions per cycle.
- Huge L1 caches: a 64KB 4-way L1 instruction cache per core (twice Zen 5's), paired with a 96KB 6-way L1 data cache, underscoring the intent to handle large instruction footprints.
- 18 execution pipes: 8 integer/branch pipes, 6 vector/FP pipes (including FP8 low-precision support, with 2 able to handle AES/SHA crypto operations), 4 load pipes, and 2 store pipes — all in pairs to support partition-based spatial multithreading.
- Aggressive out-of-order execution: memory renaming (execute dependent instructions before a load completes), value prediction (guess and verify repetitive patterns), and move elimination to extract more instruction-level parallelism.
- A graph prefetcher: targets pointer-heavy, indirection-heavy graph data by prefetching the final target memory address before the pointer is resolved — a prefetch scheme neither AMD nor Intel currently has.
It is worth taking the SPEC CPU 2026 numbers with a grain of salt: benchmarks describe peak performance under specific compilers and configurations, while real throughput, power, and stability must be validated against your actual workload. For selectors, the more interesting question is how the combination of 1.2TB/s memory bandwidth, 176 threads, and FP8 support actually behaves in AI inference scenarios.
What it means for server selection
Vera's significance goes beyond "NVIDIA made another ARM CPU." It means another heavyweight entering the ARM server ecosystem, competing head-to-head with Intel Xeon, AMD EPYC, and a growing field of Arm-based CPUs. As reviewers note, Vera is not intended to face existing processors across every general-purpose workload; it targets AI servers, and in particular agentic AI servers — leading single-core performance, high memory bandwidth, and tightly coupled parallel compute fit AI inference and agentic workloads well.
For cloud providers and hosting companies, this points to richer ARM cloud instance options and more price competition ahead; for developers, it means stronger ARM compute for the same budget, while re-evaluating software-stack compatibility on ARM.
For selectors, a few practical dimensions matter. First, the software ecosystem: ARM instances are now quite mature for containers, Kubernetes, common language runtimes, and databases, though legacy apps relying on x86-specific instructions or closed-source binaries still need real testing. Second, value for money: ARM's core density and efficiency tend to be higher, often lowering cost for always-on web, cache, and microservice workloads. Third, vendor lock-in: confirm you can migrate instance types freely within your cloud account rather than being tied to one machine type. Before migrating, run your real workload on a small ARM instance and compare benchmarks rather than trusting paper specs.
A selection scenario
Suppose you are selecting hardware for a set of agentic AI services (multi-turn tool calling, retrieval-augmented generation). The bottleneck for these workloads is usually not core count but memory bandwidth and low-latency instruction execution. Compare three options: a general-purpose x86 instance has average bandwidth per core; a high-bandwidth ARM instance in Vera's class reaches 1.2TB/s with leading single-core performance; and a Graviton-class chip wins on ecosystem maturity and price stability. If your application already runs reliably on ARM, the high-bandwidth ARM instance usually looks more attractive for inference throughput; if it depends heavily on x86 binaries, run a migration test before deciding.
16IDC Take
Server selection is entering a phase of parallel ARM-versus-x86 competition. If you're doing server selection, watch ARM instance value-for-money trends, combine cloud server pricing comparisons with server benchmarking, and for AI workloads compare GPU cloud servers. See more in the Server Selection category.
Source: https://www.servethehome.com/diving-deeper-on-nvidias-vera-cpu-new-architectural-details-and-spec-cpu-2026-benchmarks/
Reference: https://www.servethehome.com/nvidia-vera-cpu-olympus-cores-and-spec-cpu-2026-benchmarks/ (ServeTheHome analysis)